Choose how your design meets silicon.
Templates define the sharing mode, file requirements, area range, IO infrastructure, services, and delivery path for each submission.
Private die freedom or shared-chip efficiency.
Ark uses MPW: the user owns a complete die. Freighter, Cruise, and OSOC use MPC: many user designs share one chip with common IO, packaging, board, and test infrastructure.
Four starting points, one submission model.
Choose the template first so the dashboard can ask for the right file package and the calculator can estimate the right price lane.
Ark
Maximum design freedom for a private die. Best for full SoC, MCU, ASIC prototypes, accelerators, high-speed interfaces, or custom mixed-signal work.
- Design area1x1 to 20x20 mm²
- Required fileGDS
- Optional filesDEF, netlist
- Deliverybare die or package
Freighter
Small-area general-purpose shared-chip lane with 73 programmable IO interfaces and optional process IP environment.
- Design area0.1x0.1 to 2x2 mm²
- Required filesDEF + netlist
- Typical designsmall ASIC module
- Board pathavailable
Cruise
RISC-V focused shared-chip template with 36 programmable IOs, retroSoC infrastructure, SDK, and bring-up support.
- Design area0.1x0.1 to 1x1 mm²
- Required filesDEF + netlist
- Typical designRISC-V core
- SupportRTOS + tests
OSOC
Course-aligned Cruise variant for One Student One Chip milestones, using the official SoC environment and standard board support.
- Design areaassessment based
- Required filesDEF + netlist
- Typical designysyx CPU
- Incentiveeligible support
Use MPW when the chip is yours end to end.
The platform treats the uploaded GDS as the user's final die implementation. Signoff focuses on manufacturing readiness, area limits, and optional service needs.
Prepare GDS
DEF and Verilog netlist can support review but are not required.
Choose area
Private die area starts at 1 mm² and scales with project needs.
Use MPC when shared infrastructure lowers the barrier.
The user's design is integrated as IP into a template top. The shared chip provides IO, package, board, and test structures.
Prepare DEF + netlist
The platform integrates user logic into template infrastructure.
Pick slot scale
Minimum user design area starts at 0.01 mm².
Turn the chosen template into a submission.
The dashboard wizard changes file requirements automatically based on MPW or MPC mode.