Ark
Independent die for full SoC, ASIC prototype, or custom mixed-signal work.
- Design area1x1 to 20x20 mm²
- InputGDS required
ECOS55-2610 tapeout deadline: 2026-09-15
Ship Your Chip.
Set Sail with Open Silicon
Flexible templates, convenient online submission, and affordable shared tapeout paths help builders move from local design files to real ECOS55 silicon.
Launch snapshot
Mock estimates
$50 USD / ¥330 CNY
Entry price in Pricing
0.01 mm²
Minimum MPC area in Templates
Up to 100%
Open Source Incentives coupon
~6 mon
Typical tape-in to delivery WIP
MPW diePrivate chip area
MPC slotsShared chip fabric
Voyage WIPManufacturing tracked online
Primary Workflow
From prepared files to tracked silicon, one guided flow.
ChipHarbor keeps the core model simple: choose a template, submit design assets, bind a shuttle order, pass signoff, pay, then follow the Tapeout Voyage.
1
Submission
Submit Design
Upload GDS for MPW, or DEF and Verilog netlist for MPC templates.
2
Order
Create Order
Select shuttle, bind a submission, add packaging or bring-up services.
3
Signoff
Signoff Check
Track LVS, DRC, density, XOR, and engineering review status.
4
WIP
Tapeout Voyage
Follow manufacturing, packaging, board assembly, and shipping milestones.
Shuttles
An airport board for open silicon departures.
Each shuttle is a scheduled manufacturing voyage. Users can see what is boarding, what is in fabrication, and what is planned next.
FlightTemplateDeadlineStatus
ECOS55-2604Ark / MPC2026-03-18Wafer Fab
ECOS55-2607Freighter2026-06-30Boarding
ECOS55-2610All templates2026-09-15Open
ECOS55-2701Ark / Cruise2026-12-15Planned
Templates
Pick the amount of freedom your chip needs.
Ark gives a private MPW die. Freighter, Cruise, and OSOC use MPC shared-chip infrastructure to reduce entry cost and simplify bring-up.
Freighter
73 programmable IOs for small custom ASIC modules and fast prototyping.
- Design area0.1x0.1 to 2x2 mm²
- InputDEF + netlist
Cruise
RISC-V focused template with retroSoC infrastructure and board support.
- Design area0.1x0.1 to 1x1 mm²
- TargetRISC-V cores
OSOC
Course-aligned Cruise variant for One Student One Chip milestones.
- Design areaAssessment based
- SupportSDK + board
PDK
ECOS55
Open 55nm foundation for template validation.
IP
Open IP
QSPI, PSRAM, UART, PLL, SoC references.
Tools
ECOS Studio
Local flows today, cloud-native design later.
Delivery
Bring-up
Packaging, boards, SDK, and test services.
Platform
ChipHarbor
Submission, order, signoff, WIP.
Ecosystem
Open infrastructure, packaged as a product workflow.
The platform connects ECOS55, open IP, SoC references, EDA flows, signoff checks, and delivery services so users can keep familiar local tools while gaining a clear path to tapeout.
Incentives
Designed to reward open silicon builders.
Mock incentive tiers show how open-source contribution, education, and community validation could translate into coupon support during checkout.
Open Source Coupon
For qualifying public PDK, IP, EDA, documentation, or reference design contributions.
OSOC Support
Course-aligned tapeout support for verified One Student One Chip milestones.
Builder Credits
Stackable mock credits for reusable examples, bring-up reports, and community reviews.
User Dashboard
Every design and order gets a visible status trail.
Dashboard views separate design submissions from orders, then connect them through signoff, payment, and Tapeout Voyage WIP.
My Designs3
My Orders2
Coupons1
tiny-riscv-core
Cruise MPC
PassedECOS55-2607Cruise MPC
sensor-fusion-asic
Freighter MPC
PendingECOS55-2610Freighter MPC
edge-ai-mcu
Ark MPW
UnsubmittedDraftArk MPW
Final CTA
Ready to board the next open silicon shuttle?
Use the calculator for a mock quote, then submit a design package and bind it to ECOS55-2610 before the deadline.