Templates

Choose the design mode before you choose the departure.

Templates define sharing mode, design size, required files, interface assumptions, optional services, and delivery expectations.

Submit Your Design Estimate Pricing

MPW And MPC

Two sharing models, one guided submission flow.

MPW gives one user a dedicated chip. MPC places multiple isolated user designs inside one shared chip with common periphery.

MPWMulti Project Wafer

Dedicated die ownership

Ark users submit a complete GDS for a standalone die. This is best when the design needs custom area, custom chip-level architecture, or independent packaging choices.

  • Required file: GDS
  • Optional context: DEF, netlist, SDC, reports
  • User-visible concept: one design maps to one chip
MPCMulti Project Chip

Shared chip economics

Freighter, Cruise, and OSOC users submit core design resources that are integrated into a shared chip with common IO, package, board, and test structures.

  • Required files: DEF and Verilog netlist
  • Optional file: GDS if generated locally
  • User-visible concept: one design maps to an isolated chip region

Animated Schematic

Area selection made visible.

The moving highlights are self-contained CSS geometry: no external silicon assets, no protected brand material.

MPW reticle and die area

The highlighted die jumps and resizes to show custom Ark area planning inside a wafer shuttle.

MPC shared chip regions

Moving regions show isolated user areas inside a chip with shared pad ring, IO, package, and board resources.

Catalog

Four launch templates for different builder needs.

ArkMPWDedicated die

Maximum freedom for complete chips

Use Ark for complete SoC, MCU, ASIC prototype, AI accelerator, high-speed interface, or analog/mixed-signal designs that need a standalone die.

  • User design size: 1 x 1 to 20 x 20 mm²
  • Template content: no fixed chip template, supports any compliant GDS
  • Required file: GDS
  • Typical services: custom packaging, backend review, bring-up consulting
FreighterMPC73 IO

Flexible small-area shared chip

Use Freighter for small digital, analog, or mixed blocks that need generous programmable IO while sharing periphery and delivery infrastructure.

  • User design size: 0.1 x 0.1 to 2 x 2 mm²
  • Template content: 73 programmable IO interfaces
  • Required files: DEF and Verilog netlist
  • Typical designs: small ASIC modules, IO-heavy experiments, prototype accelerators
CruiseMPCRISC-V

RISC-V first shared chip path

Use Cruise when your custom contribution is a RISC-V core or accelerator inside a known SoC, SDK, board, and bring-up environment.

  • User design size: 0.1 x 0.1 to 1 x 1 mm²
  • Template content: 36 programmable IO plus retroSoC IP
  • Required files: DEF and Verilog netlist
  • Typical designs: PicoRV32 style core, RV accelerator, RTOS-capable educational SoC
OSOCMPCCourse aligned

One Student One Chip style path

Use OSOC for course-aligned CPU submissions that follow the official SoC environment and assessment expectations.

  • User design size: according to OSOC assessment requirements
  • Template content: official SoC environment, SDK, board support
  • Required files: DEF and Verilog netlist
  • Typical designs: ysyx CPU and supported course projects

Decision Aid

Template selection is the first real product decision.

NeedBest fitMinimum areaNext step
Complete standalone chipArk1 mm²Price Ark
Small custom blockFreighter0.01 mm²Submit DEF
RISC-V coreCruise0.01 mm²Submit Netlist
OSOC course projectOSOCCourse specStart OSOC