Submit Design
Upload the file package required by your template: GDS for MPW, DEF and Verilog netlist for MPC.
ECOS55-2610 tapeout deadline: 2026-09-15
Ship Your Chip.Set Sail with Open Silicon
Flexible, convenient, and affordable tapeout for builders who need a guided path from local design files to real ECOS55 silicon.
Generated ECOS55 MPW planning field
Reticle map, die slots, and layout density visualization
Mock visual
Primary Workflow
A tapeout path that behaves like a disciplined build pipeline.
Choose a template, upload the right design resources, bind the submission to a shuttle, pass signoff, pay, then track the physical voyage.
chipharbor submit --template freighter
templateFreighter MPC / 73 programmable IO
filestop.def, design.v, constraints.sdc
signoffDRC pending, LVS queued, density planned
orderBind to ECOS55-2610 before 2026-09-15
Create Order
Select a shuttle, optional services, coupon eligibility, and bind the submission to signoff.
Pass Signoff
Track DRC, LVS, layer density, XOR, and engineering review as visible order states.
Tapeout Voyage
Follow GDS ready, tapeout, wafer start, fabrication, dicing, packaging, board assembly, and shipping.
Shuttles
Departure-board clarity for real manufacturing batches.
Each shuttle works like a scheduled departure: deadline, capacity, gate, signoff state, and WIP stage are visible before you commit.
ShuttleStatusDeadlineGate
ECOS55-2610OPEN2026-09-15Gate A3
ECOS55-2702PLANNED2027-01-20Gate B1
ECOS55-2604WAFER FAB2026-04-18Line 55N
ECOS55-2511DELIVERED2025-11-06Dock 07
Templates
Start with the right amount of silicon freedom.
Ark gives you a dedicated MPW die. Freighter, Cruise, and OSOC use MPC economics to share chip infrastructure while keeping user designs isolated.
MPWDedicated die
Ark
For complete SoCs, MCUs, mixed-signal prototypes, and custom ASICs that need independent die ownership.
Area1-400 mm²
RequiredGDS
MPC73 IO
Freighter
Flexible small-area chip prototyping with programmable IO and optional board support.
Area0.01-4 mm²
RequiredDEF + netlist
MPCRISC-V
Cruise
RISC-V oriented shared-chip template with retroSoC infrastructure, SDK, and bring-up path.
Area0.01-1 mm²
RequiredDEF + netlist
MPCOSOC
OSOC
A course-aligned Cruise variant for One Student One Chip style submissions and assessments.
AreaCourse spec
RequiredDEF + netlist
Ecosystem
Open process access, practical infrastructure, and familiar local workflows.
ECOS55 Open PDK
55nm process foundation maintained with the ECOS ecosystem and foundry collaboration.
Open IP and SoC Blocks
QSPI, PSRAM, UART, PLL, retroSoC, OSOC, and reference designs become reusable launch equipment.
EDA Path
Local file upload today, cloud-native chip design tools tomorrow, tied into the same submission and order flow.
Incentives
Make open silicon contribution visible in the price.
Prototype coupon programs are mocked but shaped around the platform brief: open source contributors and OSOC learners can qualify for subsidized tapeout.
Up to 100% coupon
Open Source Incentives
Applicants can attach a public repository, contribution note, course certificate, or OSOC assessment record during order creation.
OPEN100100% qualified open-source grant
BUILDER4040% builder subsidy
OSOC-YSYX100% OSOC eligible flow
coupon review
projectopen-uart-bridge / Apache-2.0
templateFreighter MPC / 0.04 mm²
reviewMaintainer proof accepted
credit$200 prototype subsidy
User Dashboard
Designs, orders, signoff, and voyage status in one control plane.
Users can submit design resources independently, then create orders when a shuttle and service package are ready.
Mock dashboard snapshot
Open Dashboarduart-harbor-ctrlSignoff passedFreighter MPC
rv32-demo-socSignoff pendingCruise MPC
sensor-asic-a1GDS readyArk MPW
Design SubmittedActual 2026-02-18
TapeOutActual 2026-04-18
Wafer FabricationActual 2026-05-22
PackagingPlanned 2026-08-10
Final CTA
Ready to turn a local design package into shipped silicon?
Start with a template, estimate the order, or submit your design for the ECOS55-2610 departure.