Open UART Bridge
Builder: Kai Chen Lab · 0.04 mm² · 73 IO validation module.
Shuttles
Mock shuttle data shows how ChipHarbor can present historical chips, active manufacturing WIP, open seats, and planned batches with airport-grade scanability.
Historical Gallery
All entries are realistic mock data for prototype demonstration.
Builder: Kai Chen Lab · 0.04 mm² · 73 IO validation module.
Builder: Harbor University · 0.12 mm² · RISC-V core with timer and UART.
Builder: North Pier Systems · 2.4 mm² · mixed-signal sensor interface prototype.
Builder: OSOC cohort · course-aligned CPU with standard SDK bring-up.
Builder: Delta Research · 0.08 mm² · custom DSP block and shared IO test harness.
Builder: Low Tide Labs · 4.0 mm² · standalone MCU prototype with QSPI and UART.
Active Shuttle WIP
The Tapeout Voyage timeline exposes manufacturing milestones and lets a wafer fabrication node reveal mask-layer progress.
Mock active shuttle with 18 submissions across Ark, Freighter, Cruise, and OSOC templates.
58% of voyage milestones completed or active.
Open And Planned
Submit deadline 2026-09-15. Best for Freighter, Cruise, OSOC, and small Ark prototypes.
Submit deadline 2027-01-20. Early planning stage with larger Ark availability.
Submit deadline 2027-05-18. Intended for labs batching spring semester projects.