We make chip design and tapeout open, affordable, and accessible — from ideas to silicon.
About
The harbor for open silicon builders.
ChipHarbor lowers the cost, complexity, and opacity of tapeout by combining open ECOS55 infrastructure, verified templates, online signoff, and trackable delivery.
To be the harbor for the open silicon era, where every chip idea can set sail.
Values
Operating principles for a physical build platform.
The values come directly from the platform brief and are expressed here as product behavior: clarity, access, trust, shared economics, and learning loops.
Open by Default
Use open PDK, IP, SoC, EDA, and knowledge assets wherever practical.
Accessible Silicon
Reduce cost and process friction for students, labs, independent builders, and prototype teams.
Builders First
Let users keep familiar local EDA workflows while the platform guides submission and signoff.
Engineering Trust
Make shuttle state, signoff results, reports, manufacturing WIP, and delivery status visible.
Shared Voyage
Use MPW and MPC batching so many builders can share manufacturing and platform resources.
Learn, Tape Out, Iterate
Support educational paths like OSOC and encourage repeated, practical silicon learning.
Platform Focus
From procurement mystery to trackable production workflow.
ChipHarbor organizes the tapeout journey around a small set of objects: Template, Shuttle, Submission, Order, Signoff, and WIP.
platform objects
templateDefines required design files and sharing mode
shuttleDefines deadline, manufacturing batch, and delivery plan
orderBinds submission, signoff, services, payment, and WIP
voyageTracks fabrication, packaging, board, and shipping states
Lower Manufacturing Cost
MPW and MPC reuse manufacturing, periphery, packaging, boards, and testing resources.
Lower Engineering Complexity
Pre-verified templates and online signoff reduce uncertainty before manufacturing commitment.
Lower Toolchain Barriers
Open PDK, open IP, ECC, ECOS Studio, and future cloud EDA connect into the same workflow.