A harbor for open silicon builders.
ChipHarbor lowers the barrier to chip design and tapeout by combining ECOS55 process access, reusable templates, shared shuttle economics, and an online workflow for submission, signoff, orders, and delivery tracking.
Make ideas real in silicon.
We make chip design and tapeout open, affordable, and accessible — from ideas to silicon.
The first platform stage focuses on online ordering, submission management, Signoff checks, manufacturing WIP, and delivery management. Future stages connect cloud-native chip design tools to the same workflow.
Become the harbor for the open silicon era.
To be the harbor for the open silicon era, where every chip idea can set sail.
That means reducing cost, reducing engineering uncertainty, keeping local EDA workflows welcome, and making manufacturing progress visible after tape-in.
The operating principles behind the platform.
Open by Default
Support open PDKs, open IP, open SoC references, open EDA infrastructure, and reusable knowledge.
Accessible Silicon
Make real chip fabrication reachable for small teams, students, hobbyists, researchers, and first-time builders.
Builders First
Keep the workflow clear: choose a template, submit required files, create an order, pass Signoff, and track WIP.
Engineering Trust
Use pre-validated templates, explicit constraints, readable Signoff states, and WIP transparency.
Shared Voyage
Use MPW and MPC sharing models to pool manufacturing resources and lower the cost of experimentation.
Learn, Tape Out, Iterate
Turn coursework, prototypes, and open-source contributions into repeatable learning loops that reach silicon.
See the shuttles currently modeled in the prototype.
Open, active, planned, and historical shuttle data is mocked but shaped around the platform domain model.