ECOS55-2610 tapeout deadline: 2026-09-15

Ship Your Chip.Set Sail with Open Silicon

Flexible templates, convenient online submission, and affordable ECOS55 tapeout paths from tiny MPC experiments to full MPW prototypes.

Generated ECOS55 MPW layout view Self-contained canvas visual: wafer grid, reticle highlight, routing layers, and active design windows.
No external assets
Primary Workflow

One online path from design package to tracked delivery.

ChipHarbor organizes the tapeout journey around three plain objects: Submission, Order, and Tapeout Voyage.

1

Submit Design

Choose a template and upload the required GDS, DEF, or netlist resources.

Submission
2

Create Order

Bind the design to a shuttle, select services, and send it to Signoff.

Signoff
3

Track Tapeout Voyage

Follow GDS readiness, tapeout, wafer start, fabrication, package, board, and shipping states.

WIP
Shuttles

A departure board for silicon voyages.

Open, active, and planned shuttles are framed like departures: deadline, destination, capacity, and WIP status are visible before a user commits.

GateShuttleDestinationDeadlineStatus
A1Open
ECOS55-2610Ark, Freighter, Cruise, OSOC
55nm MPW/MPCPackaging and devboard options
2026-09-15Submit DDL
BOARDING
B4Planned
ECOS55-2702Freighter early access
Shared IO chipLow-cost MPC
2027-01-28Mock plan
SCHEDULED
C2Historical
ECOS55-260418 user designs
Wafer dicingDelivery WIP
2026-04-30Tape-in
IN FAB
Templates

Pick the right vessel for the design size and freedom you need.

Ark offers independent MPW die area. Freighter, Cruise, and OSOC use MPC sharing to make the first silicon iteration smaller and more affordable.

Ark

Independent die for full custom SoC, ASIC, MCU, accelerator, or mixed-signal prototypes.

MPW1-400 mm²

Freighter

Shared chip template with 73 programmable IOs for small digital or mixed-signal blocks.

MPC0.01-4 mm²

Cruise

RISC-V friendly shared platform with retroSoC infrastructure and 36 programmable IOs.

MPC0.01-1 mm²

OSOC

Course-aligned template for One Student One Chip style learning and assessment flows.

MPCCourse path
Ecosystem

Open process, reusable infrastructure, practical services.

The prototype foregrounds ECOS55, open IP, local workflow uploads, signoff checks, optional services, and platform tracking as one connected experience.

ECOS55 foundation

Open 55nm PDK ecosystem, template rules, and process-aware signoff paths.

Open IP and EDA

QSPI, PSRAM, UART, PLL, retroSoC, OSOC, ECOS Studio, and ECOS Chip Compiler pathways.

Delivery services

Bare die, packaged samples, custom board options, bring-up, RTL verification, and backend review.

Incentives

Open Source Incentives can turn contribution into tapeout credit.

Qualified open-source chip ecosystem contributors can receive discounts, with mocked coupon paths up to full sponsorship for eligible projects.

Mock incentive

Up to 100% coupon

OPEN100

For approved open-source PDK, IP, SoC, EDA, education, or OSOC-aligned contributions. Eligibility and review are mocked in this prototype.

User Dashboard

Designs and orders live together, but stay distinct.

Users can see template requirements, Signoff status, payment readiness, and the Tapeout Voyage without needing foundry vocabulary first.

My Designs3 active
HarborCore-RV32Cruise MPC - Signoff pending
Pending
CurrentSense-AFEArk MPW - GDS uploaded
Unsubmitted
QSPI-LabFreighter MPC - Passed report
Passed
Tapeout VoyageECOS55-2604-Freighter-MPC01
Design Submitted2026-04-12
TapeOut2026-05-01
Wafer FabricationIn progress
PackagingPlanned
Final CTA

Ready to reserve space on the next ECOS55 shuttle?

Mock your order, check the file requirements, and send a design package into the dashboard flow.