ECOS55-2610 tapeout deadline: 2026-09-15

Ship Your Chip.
Set Sail with Open Silicon

Flexible templates, convenient online submission, and affordable shared tapeout paths for designers who want real silicon without rebuilding the manufacturing pipeline.

Submit Your Design Explore Templates
Primary Workflow

From design package to tracked silicon order.

ChipHarbor keeps the manufacturing path legible: select a template, upload the right files, bind a shuttle, clear signoff, and follow the Tapeout Voyage.

1

Choose Template

Pick MPW freedom or MPC shared infrastructure.

Ready
2

Submit Design

Upload GDS, DEF, netlist, or package files by template.

Files checked
3

Create Order

Bind a submission to a shuttle and services.

Queued
4

Signoff

LVS, DRC, density, XOR, and rule review.

Passable
5

Tapeout Voyage

Track manufacturing, packaging, board assembly, and delivery.

Visible
Shuttles

Departure-board clarity for ECOS55 tapeout lanes.

Open and planned shuttles are shown like manufacturing departures: deadline, template lanes, and WIP state stay visible before users order.

ShuttleDeadlineTemplatesStatus
ECOS55-2610
2026-09-15
Ark / Freighter / Cruise / OSOC
Open
ECOS55-2702
2027-01-20
Freighter / Cruise / OSOC
Planned
ECOS55-2604
2026-04-30
Ark / Freighter
Wafer Fabrication
ECOS55-2511
2025-11-08
Cruise / OSOC
Packaging
View Shuttle Gallery Price a Seat
Templates

Pick the amount of infrastructure you want to share.

Ark gives you a full MPW die. Freighter, Cruise, and OSOC use MPC sharing to make tiny, low-cost designs practical.

Ark

MPW

A dedicated die for custom SoC, ASIC, MCU, accelerator, or mixed-signal prototypes.

  • Design size1x1-20x20 mm²
  • FreedomMaximum

Freighter

MPC

Small-area custom logic with 73 programmable IOs and shared tapeout infrastructure.

  • Design size0.01-4 mm²
  • Best forASIC modules

Cruise

MPC

RISC-V focused designs with retroSoC infrastructure, SDK, and bring-up support.

  • Design size0.01-1 mm²
  • Best forRISC-V cores

OSOC

MPC

A special Cruise lane for One Student One Chip learners and official SoC packages.

  • Design sizeCourse rules
  • IncentiveEligible free run
Explore Templates
Ecosystem

Open silicon rails for builders who still want control.

ChipHarbor builds around ECOS55, open IP, reusable templates, and workflow compatibility rather than forcing everyone into one editor.

ECOS55 PDK

Open 55 nm process infrastructure maintained with the ECOS ecosystem and manufacturing partners.

Open IP and SoC

QSPI, PSRAM, UART, PLL, retroSoC, OSOC, and reference bring-up patterns feed template readiness.

EDA Compatibility

Use local flows today. Future ECOS Studio and cloud-native tools can connect into the same submission path.

Delivery Trail

Orders keep signoff status, payment state, manufacturing WIP, packaging, board assembly, and shipping together.

Incentives

Open source work can lower the ticket price.

Mocked incentive rules show how open PDK, IP, SoC, EDA, and education contributors could receive coupons up to a fully covered MPC entry order.

Try Coupon Pricing
OPEN100

For approved open silicon ecosystem contributors.

100%
OPEN50

For public reference designs and verified educational use.

50%
OSOC2026

For qualified One Student One Chip tapeout assessments.

100%
User Dashboard

Designs and orders stay in one operating view.

Users can keep submitted design packages separate from paid manufacturing orders, then bind them when signoff and shuttle timing are ready.

tiny-dsp-v3

Freighter MPC · Signoff passed

Ready to pay
rv32-lab-core

Cruise MPC · Pending platform checks

Signoff pending
ORD-2610-018

ECOS55-2610 · Tapeout Voyage queued

Order created
Open Dashboard
Final CTA

Ready to put a design on the next shuttle?

Start with a submission, price the order, or compare templates before the ECOS55-2610 deadline.

Submit Your Design Open Pricing Calculator