Multi Project Wafer
Ark allocates a dedicated die for one user design. It is the best fit when you need full chip freedom, custom dimensions, or a complete SoC/ASIC prototype.
- User boundaryDedicated die
- Required packageGDS
- Minimum area1 mm²
Template Registry
Choose the verified route your design package should follow.
Templates define sharing mode, area range, required upload files, IO expectations, service compatibility, and the signoff checklist that turns a local design into a manufacturable submission.
Sharing Modes
MPW gives you a die. MPC gives you a protected slot on a shared chip.
Both modes use the same platform objects: Template, Shuttle, Submission, Order, Signoff, and Tapeout Voyage.
Multi Project Chip
Freighter, Cruise, and OSOC share pad rings, test structures, boards, and package options so tiny designs can enter a shuttle at much lower cost.
- User boundaryIsolated slot
- Required packageDEF + netlist
- Minimum area0.01 mm²
Animated Schematics
Inspect the physical difference before choosing a template.
The visuals are generated locally on canvas for this prototype; they are schematic, not foundry layout data.
Ark MPW: one submission owns the die outline.
Area, package, and optional services scale with the dedicated design window.
Freighter, Cruise, OSOC MPC: many submissions share chip infrastructure.
Slots are integrated under a shared top level with protected routing and IO policy.
Catalog
Four routes from maximum freedom to course-aligned submission.
Area ranges, IO counts, and service fit are realistic mock assumptions and should be checked by engineering owners before public launch.
MPW
Ark
template/ark
Dedicated die for commercial ASIC prototypes, complete SoCs, MCUs, accelerators, high-speed interface chips, and custom mixed-signal work.
- User area1x1-20x20 mm²
- RequiredGDS
- OptionalDEF / netlist / SDC
- Best fitcustom chip
MPC
Freighter
template/freighter
Shared chip route with programmable IO for small ASIC, mixed-signal module, and fast prototype builders who want low entry cost.
- User area0.1x0.1-2x2 mm²
- RequiredDEF + Verilog netlist
- IO73 programmable
- Best fitsmall ASIC
MPC
Cruise
template/cruise
RISC-V oriented route with retroSoC infrastructure, board support, SDK references, and bring-up guidance for small CPU designs.
- User area0.1x0.1-1x1 mm²
- RequiredDEF + Verilog netlist
- IO36 programmable
- Best fitRISC-V core
MPC
OSOC
template/osoc
Education-aligned route for One Student One Chip style projects using a standard SoC environment, SDK, board flow, and incentive review.
- User areaby review
- Requiredcourse package
- Coupon patheligible
- Best fitstudent SoC
template/checks.yml
shared signoff surface
Design rule report
requiredLayout versus schematic
requiredDensity and fill window
requiredFinal data comparison
reviewedPackage and board fit
by service