Multi Project Wafer
You own the whole die area for a complete chip, SoC, ASIC prototype, or custom mixed-signal experiment.
Templates
Choose the design envelope, then bring your own circuit.
Ark, Freighter, Cruise, and OSOC model two shared manufacturing strategies: MPW for an independent die and MPC for a shared chip with verified platform infrastructure.
MPW And MPC
Two ways to share a shuttle.
MPW gives you a full die. MPC lets multiple user designs share one chip, IO, package, board, and test structures.
Multi Project Chip
Your design becomes a protected region inside a shared chip, lowering cost through reusable platform infrastructure.
Template Catalog
Four mocked routes into ECOS55.
Maximum freedom
Independent die for complete SoC, MCU, ASIC, accelerator, or custom mixed-signal prototypes.
- Area1x1 to 20x20 mm²
- FilesGDS required
- Mock price$4,400/mm²
Flexible small area
Shared chip with 73 programmable IO interfaces for small digital or analog prototypes.
- Area0.01 to 4 mm²
- FilesDEF + netlist
- Mock entry$50
RISC-V path
Shared chip with 36 programmable IO interfaces and retroSoC infrastructure.
- Area0.01 to 1 mm²
- FilesDEF + netlist
- Mock entry$50
Course-aligned
A Cruise-based path for One Student One Chip style SoC submissions and SDK support.
- AreaCourse rules
- FilesDEF + Verilog
- CouponOSOC100 eligible
Animated Schematic
Small designs move inside a shared chip.
The MPC visual shows a core area, pad ring, programmable IO blocks, and multiple highlighted user regions resizing inside proportional geometry.
For Ark MPW, the user area can grow into a full independent die. For Freighter, Cruise, and OSOC, your region stays inside a shared chip boundary while the template supplies platform infrastructure.
Submit With A Template