Submit Design
Choose Ark, Freighter, Cruise, or OSOC. Upload the required GDS, DEF, or Verilog netlist assets for signoff.
ECOS55-2610 tapeout deadline: 2026-09-15
Ship Your Chip.
Set Sail with Open Silicon
Flexible, convenient, and affordable tapeout for builders who want a real chip without negotiating the whole semiconductor maze.
Pick a verified template, upload the files your flow already produces, bind a shuttle, clear signoff, and track the voyage from tape-in to delivery.
Primary Workflow
One clean voyage from local design files to delivered silicon.
ChipHarbor keeps the user model small: Template, Shuttle, Submission, Order, and Tapeout Voyage.
Create Order
Bind the submission to an active shuttle, pick package, board, and bring-up services, then preview the price.
Pass Signoff
Platform checks LVS, DRC, density, XOR, and template constraints before payment opens.
Track Voyage
Follow tapeout, wafer start, fabrication, dicing, packaging, board assembly, and shipping in one timeline.
Shuttles
Departure boards for silicon.
Every shuttle behaves like a scheduled voyage: deadline, capacity, signoff gate, and WIP status stay visible.
The ECOS55-2610 shuttle is open for submissions, with a September 15, 2026 tapeout deadline and a typical six-month tape-in to delivery window.
View Shuttle Board
ShuttleGateDeadlineStatus
ECOS55-2610A32026-09-15Boarding
ECOS55-2612B12026-11-30Open Soon
ECOS55-2703C22027-02-20Planned
ECOS55-2606Arrivals2026-05-08Fabrication
Templates
Start with the right amount of freedom.
Ark gives a full independent MPW die. Freighter, Cruise, and OSOC share a verified MPC chip around reusable IO, packages, boards, and test structures.
Full die
For custom SoCs, ASIC prototypes, accelerators, and mixed-signal designs from 1x1 to 20x20 mm².
Small area
For 0.1x0.1 mm² and up, with 73 programmable IO interfaces and flexible user logic.
Ecosystem
Built around open ECOS55 infrastructure.
ECOS55
A 55nm open PDK foundation maintained with foundry collaboration.
Reusable blocks
QSPI, PSRAM, UART, PLL, and platform IP become practical starting points.
Reference systems
retroSoC, OSOC, SDKs, boards, and bring-up paths help designs close the loop.
Tool flow
ECOS Studio and ECOS Chip Compiler point toward cloud-native design work.
Incentives
Open work should have a shorter swim to silicon.
Mock incentive programs show how qualified open-source builders, course projects, and OSOC learners could receive significant tapeout support.
Coupons such as OPEN50, OPEN100, and OSOC100 are used in this prototype to model discount eligibility, review, and purchase behavior.
Try Coupon PricingUp to 100% coupon
For qualifying open-source ecosystem contributions after review.
Student voyage
A mocked free-tapeout path for eligible One Student One Chip submissions.
Dashboard Preview
Mock logged in as Ada| Design | Template | Signoff | Voyage |
|---|---|---|---|
| vector-spark.gds | Freighter | Passed | Wafer Start |
| tiny-rv-core.def | Cruise | Pending | Awaiting Signoff |
| osoc-ysyx-netlist.v | OSOC | Unsubmitted | Draft |
User Dashboard
The workbench after the promise.
My Designs tracks submissions and signoff. My Orders tracks payment, services, and Tapeout Voyage WIP.
The prototype dashboard includes Submit Design and Create Order wizard modals, so the landing CTAs connect to the real platform workflow.
Open DashboardFinal CTA
Your chip idea is closer than a foundry contract.
Start with a template, price the voyage, and submit when your files are ready.